systemverilog

Always assert your randomizations

Mon 18 March 2013 by Tsvi Mostovicz / Verification

Today I was bitten twice by the same issue: randomization.

When you randomize something you should always assert the randomization. This will allow you to find the source of the problem much quicker. I lament the fact that UVM sequence macros do not assert the randomization by default. Instead they …

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