Always assert your randomizations

by Tsvi Mostovicz - Mon 18 March 2013
Tags #assertions #systemverilog #random
Reading time: 0 minutes, 28 seconds

Today I was bitten twice by the same issue: randomization.

When you randomize something you should always assert the randomization. This will allow you to find the source of the problem much quicker. I lament the fact that UVM sequence macros do not assert the randomization by default. Instead they issue a warning with id RNDZFLD.

By the way, in case the randomization failed, you can rerun the simulation with the -solvefaildebug switch if running Modelsim/Questa. This will give you an idea why the solver was unable to satisfy your constraints.

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