UVM

The highs and lows of UVM

Thu 19 June 2014 by Tsvi Mostovicz / Verification

I just read this article (Accellera DAC 2014 Breakfast—What Engineers Really Think About UVM). They hit a few interesting points.

I'd like to add another few points that I think were missed in this discussion.

The highs

UVM helps the developer create reusable components (though I have seen UVM …

UVM register model coverage woes - part 2

Mon 24 March 2014 by Tsvi Mostovicz / Verification

So after I described my troubles with the UVM register model's coverage in my previous post, I revisited the issue in a slightly different context and discovered the current solution was rather lacking.

Register block coverage

In the previous example, coverage was taken for a value written via the register …

My issues with uvm_reg's predict method

Mon 29 April 2013 by Tsvi Mostovicz / Verification

A couple of weeks ago, I created a status register callback class.

The purpose of it was to create a built-in scoreboard allowing me to predict the value of a status register based on the known status signal's input.

I'll maybe post the code in a sometime in the future …

Don't use null as a sequencer argument to uvm_reg_sequence

Sun 17 March 2013 by Tsvi Mostovicz / Verification

Back when I started using UVM, I had no use for a register model for the specific unit I was testing. As such, sequences were written which needed a sequencer which would hand the items in the sequence to the driver.

Over time, we moved to use the register model …