coverage

UVM register model coverage woes - part 2

Mon 24 March 2014 by Tsvi Mostovicz / Verification

So after I described my troubles with the UVM register model's coverage in my previous post, I revisited the issue in a slightly different context and discovered the current solution was rather lacking.

Register block coverage

In the previous example, coverage was taken for a value written via the register …

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The crooked ways of UVM's register model's coverage methods

Mon 02 September 2013 by Tsvi Mostovicz / Verification

"Welcome to the world of Coverage"

I have been dabbling now for a couple of weeks with coverage. Working my way through the SV LRM, looking at some examples and running a few simple cases.

My first case was some protocol coverage. We wanted to verify certain types of traffic …

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